View MB90F822B_4962584.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FUJITSU MICROELECTRONICS DATA SHEET
DS07-13751-2E
16-bit Microcontroller
CMOS
F2MC-16LX MB90820B Series
MB90822B/823B/F822B/F823B/F828B/V820B
DESCRIPTION
The MB90820B series is a line of general-purpose, Fujitsu 16-bit microcontrollers designed for process control applications which require high-speed real-time processing, such as consumer products. While inheriting the AT architecture of the F2MC family, the instruction set for the F2MC-16LX CPU core of the MB90820B series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90820B series has an on-chip 32-bit accumulator which enables processing of long-word data. The peripheral resources integrated in the MB90820B series include : an 8/10-bit A/D converter, 8-bit D/A converters, UARTs (SCI) 0, 1, multi-functional timer (16-bit free-run timer, input capture units (ICUs) 0 to 3, output compare units (OCUs) 0 to 5, 16-bit PPG timer 0, waveform generator), 16-bit PPG timer 1, 2, PWC 0, 1, 16-bit reload timer 0, 1 and DTP/external interrupt. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
FEATURES
* Minimum execution time of instruction : 42 ns / 4 MHz oscillation (uses PLL clock multiplication) maximum multiplier = 6 * Maximum memory space 16 M bytes, Linear/bank access * Instruction set optimized for controller applications Supported data types : bit, byte, word, and long-word types Standard addressing modes : 23 types 32-bit accumulator enhancing high-precision operations Signed multiplication/division instructions and enhanced RETI instructions (Continued)
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright(c)2008-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.1
MB90820B Series
(Continued) * Enhanced high level language (C) and multi-tasking support instructions Use of a system stack pointer Symmetrical instruction set and barrel shift instructions * Program patch function (for two address pointers) * Increased execution speed : 4-byte instruction queue * Powerful interrupt function Up to eight priority levels programmable External interrupt inputs : 8 channels * Automatic data transmission function independent of CPU operation Up to 16 channels for the extended intelligent I/O service DTP request inputs : 8 channels * Internal ROM Flash memory : 64 K/128 K bytes with flash security MASK ROM : 64 K/128 K bytes * Internal RAM Evaluation product : 16 K bytes Flash memory : 4 K/8 K bytes MASK ROM : 4 K bytes * General-purpose ports Up to 66 channels (ports where pull-up resistor can be configured : 32 channels) * A/D Converter (RC) : 16 channels 8/10-bit resolution selectable Conversion time : Min 3 s (24 MHz operation, including sampling time) * 8-bit D/A Converter : 2 channels * UART : 2 channels * 16-bit PPG timer : 3 channels Mode switching function provided (PWM mode or one-shot mode) ch.0 can be worked with multi-functional timer or independently * 16-bit reload timer : 2 channels * 16-bit PWC timer : 2 channels * Clock supervisor * Multi-functional timer Input capture : 4 channels Output compare with selectable buffer : 6 channels Free-run timer with up or up-down mode selection and selectable buffer: 1 channel 16-bit PPG timer : 1 channel Waveform generator : (16-bit timer : 3 channels, 3-phase waveform or dead time) * Time-base timer/watchdog timer : 18-bit * Low-power consumption mode : Sleep mode Stop mode CPU intermittent operation mode * Package : LQFP-80 (FPT-80P-M21 : 0.50 mm pitch) LQFP-80 (FPT-80P-M22 : 0.65 mm pitch) QFP-80 (FPT-80P-M06 : 0.80 mm pitch) * CMOS technology
2
DS07-13751-2E
MB90820B Series
PRODUCT LINEUP
Part number Item Classification ROM size RAM size MB90V820B Evaluation product -- 16 K bytes MB90F822B MB90F823B MB90F828B MB90822B MB90823B
Flash memory product with flash security 64 K bytes 128 K bytes 128 K bytes 8 K bytes 4 K bytes
MASK ROM product 64 K bytes 128 K bytes
4 K bytes
CPU function
Number of instruction : 351 Minimum execution time : 42 ns / 4 MHz (PLL x 6) Addressing mode : 23 Data bit length : 1, 8, 16 bits Maximum memory space: 16 M bytes I/O port (CMOS) : 66 Pulse width counter timer : 2 channels Timer function (select the counter timer from three internal clocks) Various pulse width measuring function ("H" pulse width, "L" pulse width, rising edge to falling edge period, falling edge to rising edge period, rising edge to rising edge period and falling edge to falling edge period) UART : 2 channels With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selected and used. Transmission can be one-to-one (bidirectional communication) or one-to-n (master-slave communication). Reload timer : 2 channels Reload mode, single-shot mode or event count mode selectable PPG timer : 3 channels PWM mode or single-shot mode selectable Ch.0 can be worked with multi-functional timer or independently. 16-bit free-run timer with up or up-down mode selection and buffer : 1 channel 16-bit output compare : 6 channels 16-bit input capture : 4 channels 16-bit PPG timer : 1 channel Waveform generator (16-bit timer : 3 channels, 3-phase waveform or dead time) 8/10-bit resolution (16 channels) Conversion time : Min 3 s (24 MHz internal clock, including sampling time) 8-bit resolution (2 channels) 8 independent channels Interrupt trigger : Rising edge, falling edge, "L" level or "H" level No Yes No
I/O port
PWC
UART
16-bit reload timer 16-bit PPG timer Multi-functional timer (for AC/DC motor control) 8/10-bit A/D converter 8-bit D/A converter DTP/External interrupt Clock supervisor Low-power consumption
Stop mode / Sleep mode / CPU intermittent operation mode (Continued)
DS07-13751-2E
3
MB90820B Series
(Continued) Part number MB90V820B Item Package PGA-299
MB90F822B
MB90F823B
MB90F828B
MB90822B
MB90823B
LQFP-80 (FPT-80P-M21 : 0.50 mm pitch) LQFP-80 (FPT-80P-M22 : 0.65 mm pitch) QFP-80 (FPT-80P-M06 : 0.80 mm pitch) 3.5 V to 5.5 V : Normal operation when A/D converter and D/A converter are not used 4.0 V to 5.5 V : Normal operation when D/A converter is not used 4.5 V to 5.5 V : Normal operation when A/D converter and D/A converter are used CMOS
Power supply voltage for operation
4.5 V to 5.5 V*1
Process Emulator power supply*2 Included
*1 : MB90V820B is operating guaranteed temperature 0 C to + 25 C. *2 : Configured by a jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply switching) about details.
PACKAGE AND CORRESPONDING PRODUCTS
Package PGA-299 FPT-80P-M21 FPT-80P-M22 FPT-80P-M06 : Available X : Not available Note: For more information about each package, refer to " PACKAGE DIMENSIONS". X X X MB90V820B MB90F822B X MB90F823B X MB90F828B X MB90822B X MB90823B X
4
DS07-13751-2E
MB90820B Series
DIFFERENCES AMONG PRODUCTS
Memory Size In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration. * The MB90V820B does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. * In the MB90V820B, images from FF8000H to FFFFFFH are mapped to bank 00, and FE0000H to FF7FFFH are mapped to bank FE and bank FF only. (This setting can be changed by configuring the development tool.) * In the MB90822B/F822B/F828B, images from FF8000H to FFFFFFH are mapped to bank 00, and FF0000H to FF7FFFH are mapped to bank FF only. In the MB90823B/F823B/F828B, images from FF8000H to FFFFFFH are mapped to bank 00, and FE0000H to FF7FFFH are mapped to bank FE and bank FF only. Clock Supervisor Function The clock supervisor is built-in in MB90F828B only. Note that the evaluation products and products actually used are different when evaluating evaluation products. Please contact the sales representatives for more information on evaluation of this function. Modify ROM data The registers include this function between 001FF0H and 001FF5H which overlap the RAM area of MB90F828B. Do not access to the RAM when using this function in MB90F282B.
DS07-13751-2E
5
MB90820B Series
PIN ASSIGNMENT
(TOP VIEW)
P70/DA0/AN8 P71/DA1/AN9 P72/SIN1/AN10 P73/SOT1/AN11 P74/SCK1/AN12 P75/FRCK/AN13 P76/IN0/AN14 P77/IN1/AN15 P80/IN2 P81/IN3 P82/RTO0(U) * P83/RTO1(X) * P84/RTO2(V) * P85/RTO3(Y) * P86/RTO4(W) * P87/RTO5(Z) * 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
AVR AVcc AVss P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P51/INT7 P50/PPG2 P47/PWO1 P46/PWI1 P45/SIN0 P44/SOT0 P43/SCK0 RST P42/TO0 P41/TIN0 Vss X0 X1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
QFP-80
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
C Vss Vcc P00 * P01 * P02 * P03 * P04 * P05 * P06/PWI0 * P07/PWO0 * P10/INT0/DTTI P11/INT1 P12/INT2 P13/INT3 P14/INT4 P15/INT5 P16/INT6 P17 P20/TIN1 P21/TO1 P22 Vcc P23
* : High current pin. (Continued)
6
MD0 MD1 MD2 P40/PPG1 P37/PPG0 P36 P35 P34 P33 P32 P31 P30 P27 P26 P25 P24
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
(FPT-80P-M06)
DS07-13751-2E
MB90820B Series
(Continued) (TOP VIEW)
AVcc AVR P70/DA0/AN8 P71/DA1/AN9 P72/SIN1/AN10 P73/SOT1/AN11 P74/SCK1/AN12 P75/FRCK/AN13 P76/IN0/AN14 P77/IN1/AN15 P80/IN2 P81/IN3 P82/RTO0(U) * P83/RTO1(X) * P84/RTO2(V) * P85/RTO3(Y) * P86/RTO4(W) * P87/RTO5(Z) * C Vss 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
AVss P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P51/INT7 P50/PPG2 P47/PWO1 P46/PWI1 P45/SIN0 P44/SOT0 P43/SCK0 RST P42/TO0 P41/TIN0 Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
LQFP-80
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
Vcc P00 * P01 * P02 * P03 * P04 * P05 * P06/PWI0 * P07/PWO0 * P10/INT0/DTTI P11/INT1 P12/INT2 P13/INT3 P14/INT4 P15/INT5 P16/INT6 P17 P20/TIN1 P21/TO1 P22
* : High current pin.
DS07-13751-2E
X0 X1 MD0 MD1 MD2 P40/PPG1 P37/PPG0 P36 P35 P34 P33 P32 P31 P30 P27 P26 P25 P24 P23 Vcc
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
(FPT-80P-M22) (FPT-80P-M21)
7
MB90820B Series
PIN DESCRIPTION
Pin no. LQFP *1 21, 22 17 59 to 54 53 52 QFP *2 23, 24 19 61 to 56 55 54 Pin name X0,X1 RST P00 to P05 P06 PWI0 P07 PWO0 P10 INT0 51 53 DTTI P11 to P16 INT1 to INT6 P17 P20 TIN1 P21 TO1 P22 to P27 P30 to P36 P37 PPG0 P40 PPG1 P41 TIN0 P42 TO0 D I/O circuit *3 A B C C C Pin status during reset Oscillating Oscillation pins. Reset input External reset input pin. General-purpose I/O ports. General-purpose I/O port. PWC ch.0 signal input pin. General-purpose I/O port. PWC ch.0 signal output pin. General-purpose I/O port. External interrupt request input ch.0 pin. RTO0 to RTO5 pins for fixed-level input. This function is enabled when the waveform generator specifies its input bits. General-purpose I/O ports. External interrupt request input ch.1 to ch.6 pins. General-purpose I/O port. General-purpose I/O port. Port input External clock input pin for reload timer ch.1. General-purpose I/O port. Event output pin for reload timer ch.1. General-purpose I/O ports. General-purpose I/O ports. General-purpose I/O port. Output pin for PPG timer ch.0. General-purpose I/O port. Output pin for PPG timer ch.1. General-purpose I/O port. External clock input pin for reload timer ch.0. General-purpose I/O port. Event output pin for reload timer ch.0. (Continued) Function
50 to 45 44 43 42 41, 39 to 35 34 to 28 27 26 19 18
52 to 47 46 45 44 43, 41 to 37 36 to 30 29 28 21 20
D D D D D E E F F F
8
DS07-13751-2E
MB90820B Series
Pin no. LQFP *1 16 15 14 13 12 11 10 9 to 2 QFP *2 18 17 16 15 14 13 12 11 to 4 Pin name P43 SCK0 P44 SOT0 P45 SIN0 P46 PWI1 P47 PWO1 P50 PPG2 P51 INT7 P60 to P67 AN0 to AN7 P70, P71 78, 77 80, 79 DA0, DA1 AN8, AN9 P72 76 78 SIN1 AN10 P73 75 77 SOT1 AN11 P74 74 76 SCK1 AN12 P75 73 75 FRCK AN13
I/O circuit *3 F F G F F F F H
Pin status during reset
Function General-purpose I/O port. Serial clock I/O pin for UART ch.0. General-purpose I/O port. Serial data output pin for UART ch.0. General-purpose I/O port. Serial data input pin for UART ch.0. General-purpose I/O port. PWC ch.1 signal input pin. General-purpose I/O port. PWC ch.1 signal output pin. General-purpose I/O port. Output pin for PPG timer ch.2. General-purpose I/O port. External interrupt request input ch.7 pin. General-purpose I/O ports. A/D converter analog input pins. General-purpose I/O ports. D/A converter analog output pins. A/D converter analog input pins. General-purpose I/O port.
Port Input
I
J Analog input K
Serial data input pin for UART ch.1. A/D converter analog input pin. General-purpose I/O port. Serial data output pin for UART ch.1. A/D converter analog input pin. General-purpose I/O port.
K
Serial clock I/O pin for UART ch.1. A/D converter analog input pin. General-purpose I/O port.
K
External clock input pin for free-run timer. A/D converter analog input pin. (Continued)
DS07-13751-2E
9
MB90820B Series
(Continued) Pin no. LQFP *1 QFP *2 Pin name P76, P77 72, 71 74, 73 IN0, IN1 AN14, AN15 70, 69 72, 71 P80, P81 IN2, IN3 P82 to P87 68 to 63 25 24, 23 80 79 1 20, 61 40, 60 62 70 to 65 27 26, 25 2 1 3 22, 63 42, 62 64 RTO0 (U) to RTO5 (Z) MD2 MD1, MD0 AVCC AVR AVSS Vss Vcc C L M N F K Analog input
I/O circuit *3
Pin status during reset
Function General-purpose I/O ports. Trigger input pins for input capture ch.0, ch.1. A/D converter analog input pins. General-purpose I/O ports.
Trigger input pins for input capture ch.2, ch.3. Port input General-purpose I/O ports. Waveform generator output pins. (U) to (Z) represent the coils for controlling a 3-phase motor. Mode input Input pin for operation mode specification. Input pins for operation mode specification. Analog power supply pin. Vref + pin for the A/D converter. Vref - is fixed to AVss internally. Analog power supply (Ground) pin. Power (Ground) pins. Power pins. Connect pin for smoothing capacitor to stabilize internal power supply.
*1 : FPT-80P-M21, FPT-80P-M22 *2 : FPT-80P-M06 *3 : Refer to " I/O CIRCUIT TYPE" for details on the I/O circuit types.
10
DS07-13751-2E
MB90820B Series
I/O CIRCUIT TYPE
Classification A
X1 P-ch N-ch
Type
Clock input
Remarks Oscillation feedback resistor : approx. 1 M
X0
Standby control signal
B
R
* Hysteresis input * Pull-up resistor : approx. 50 k * CMOS output * Hysteresis input * Selectable pull-up resistor : approx. 50 k * IOL = 12 mA
C
R
P-ch
Pull-up control P-ch Digital output Digital output
N-ch
Hysteresis input Standby mode control
D
R
P-ch
Pull-up control P-ch Digital output Digital output
* CMOS output * Hysteresis input * Selectable pull-up resistor : approx. 50 k * IOL = 4 mA
N-ch
Hysteresis input Standby mode control
E
R
P-ch
Pull-up control P-ch Digital output Digital output
* * * *
CMOS output CMOS input With pull-up control IOL = 4 mA
N-ch
CMOS input Standby mode control
(Continued) DS07-13751-2E 11
MB90820B Series
Classification F
P-ch
Type
Digital output Digital output
Remarks * CMOS output * Hysteresis input * IOL = 4 mA
N-ch
Hysteresis input Standby mode control
G
P-ch Digital output Digital output
N-ch
* CMOS output * Hysteresis input * CMOS input (selectable for UART ch.0 data input pin) * IOL = 4 mA
Hysteresis input
CMOS input
Standby mode control
H
P-ch Digital output Digital output
* * * *
CMOS output CMOS input Analog input IOL = 4 mA
N-ch
CMOS input Analog input control Analog input
I
P-ch Digital output Digital output
N-ch
* * * * *
CMOS output Hysteresis input Analog output Analog input IOL = 4 mA
Hysteresis input Analog I/O control Analog output Analog input
(Continued)
12
DS07-13751-2E
MB90820B Series
(Continued) Classification J
P-ch Digital output Digital output
Type
Remarks * CMOS output * Hysteresis input * CMOS input (selectable for UART ch.1 data input pin) * IOL = 4 mA
N-ch
Hysteresis input
CMOS input Analog input control Analog input
K
P-ch Digital output Digital output
* * * *
CMOS output Hysteresis input Analog input IOL = 4 mA
N-ch
Hysteresis input Analog input control Analog input
L
P-ch Digital output Digital output
* CMOS output * Hysteresis input * IOL = 12 mA
N-ch
Hysteresis input Standby mode control
M
R
MASK ROM / evaluation product * Hysteresis input * Pull-down resistor : approx. 50 k Flash memory product * CMOS input * No pull-down resistor MASK ROM / evaluation product * Hysteresis input Flash memory product * CMOS input
N
DS07-13751-2E
13
MB90820B Series
HANDLING DEVICES
Special care is required for the following when handling the device : * Preventing latch-up * Stabilization of supply voltage * Treatment of unused pins * Using external clock * Power supply pins (VCC /VSS ) * Pull-up/pull-down resistors * Crystal Oscillator Circuit * Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs * Connection of Unused Pins of A/D Converter * Notes on turning the power on * Notes on During Operation of PLL Clock Mode
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions : * A voltage higher than VCC or lower than VSS is applied to an input or output pin. * A voltage higher than the rated voltage is applied between VCC and VSS pins. * The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. In using the devices, take sufficient care to avoid exceeding maximum ratings. For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVR) exceed the digital power-supply voltage.
2. Stabilization of supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply voltage operation range. Therefore, the VCC supply voltage should be stabilized. For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at commercial frequencies (50 Hz/60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
3. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 k. Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection.
4. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open. MB90820B series
X0
Open
X1
14
DS07-13751-2E
MB90820B Series
5. Power supply pins (VCC/VSS)
* If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up. To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally. * Connect VCC and VSS pins to the device from the current supply source at a low impedance. * As a measure against power supply noise, connect a capacitor of about 0.1 F as a bypass capacitor between VCC and VSS pins in the vicinity of VCC and VSS pins of the device.
VCC VSS
VCC VSS VCC
VSS
MB90820B Series
VCC
VCC VSS
VSS
6. Pull-up/pull-down resistors
The MB90820B series does not support internal pull-up/pull-down resistors option (Port 0 to Port 3 : built-in pullup resistors) . Use external components where needed.
7. Crystal oscillator circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic oscillator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits while you design a printed circuit board. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground area for stabilizing the operation.
8. Turning-on sequence of power supply to A/D converter and D/A converter, and analog inputs
Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVR) and analog inputs (AN0 to AN15) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter power supply, D/A converter power supply, and analog inputs. In this case, make sure that the voltage not exceed AVR or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable).
9. Pin connections when A/D converter and D/A converter are unused
When the A/D converter and D/A converter are not used, connect AVCC = VCC, AVSS = AVRH = AVRL = VSS.
DS07-13751-2E
15
MB90820B Series
10. Notes on turning the power on
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during power on at 50 s or more (0.2 V to 2.7 V) .
11. Notes on During Operation of PLL Clock Mode
If the PLL clock mode is selected, the microcontroller may continue to operate at the free-running frequency of the self-oscillating circuit within the PLL even if the external oscillator is disconnected or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
12. Internal CR Oscillation Circuit
Rating Min 50 Typ 100 Max 200 100
Parameter Oscillation frequency Oscillation stabilization waiting time
Symbol fRC tstab
Unit kHz s
16
DS07-13751-2E
MB90820B Series
SECTOR CONFIGURATION OF FLASH MEMORY
The flash memory has the sector configuration illustrated below. The addresses in the illustration are the upper and lower addresses of each sector. When 512K bits flash memory is accessed from the CPU, SA0 to SA3 are allocated in the FF bank.
Flash memory SA3 (16K bytes)
CPU address FFFFFFH FFC000H FFBFFFH FFA000H
*Writer address 7FFFFH 7C000H 7BFFFH 7A000H 79FFFH 78000H 77FFFH 70000H
SA2 (8K bytes)
SA1 (8K bytes)
FF9FFFH FF8000H
SA0 (32K bytes)
FF7FFFH FF0000H
When 1024K bits flash memory is accessed from the CPU, SA0 to SA4 are allocated in the FE and FF bank.
Flash memory SA4 (16K bytes)
CPU address FFFFFFH FFC000H FFBFFFH FFA000H
*Writer address 7FFFFH 7C000H 7BFFFH 7A000H 79FFFH 78000H 77FFFH 70000H 6FFFFH 60000H
SA3 (8K bytes)
SA2 (8K bytes)
FF9FFFH FF8000H
SA1 (32K bytes)
FF7FFFH FF0000H FEFFFFH FE0000H
SA0 (64K bytes)
* : The writer address is the address corresponding to the CPU address when writing data from a parallel flash memory writer. Use the writer address when programming or erasing using a general-purpose parallel writer.
DS07-13751-2E
17
MB90820B Series
BLOCK DIAGRAM
CR oscillation circuit *1
X0 X1
Clock control circuit, monitor circuit *1 Reset circuit (Watchdog timer) Interrupt controller
CPU
F MC-16LX core
2
VSS x 2, VCC x 2, MD0 to MD2, C Time-base timer
Delayed interrupt generator
7
Other pins
RST
Multi-functional timer
P51/INT7 P16/INT6 to P11/INT1 P45/SIN0 P44/SOT0 P43/SCK0
P72/SIN1/AN10 P73/SOT1/AN11 P74/SCK1/AN12 6 8
P30 to P36 P37/PPG0
DTP/External interrupt
16-bit PPG timer (ch.0) 16-bit input capture (ch.0 to ch.3) 16-bit free-run timer 16-bit output compare (ch.0 to ch.5)
4 4
UART (ch.0) UART (ch.1) 16-bit PPG (ch.1) 16-bit PPG (ch.2) PWC (ch.1)
P76/IN0/AN14 P77/IN1/AN15 P80/IN2 P81/IN3
P75/FRCK/AN13
P40/PPG1
F2MC-16LX bus
P82/RTO0 (U) *2 P83/RTO1 (X) *2 P84/RTO2 (V) *2 P85/RTO3 (Y) *2 P86/RTO4 (W) *2 P87/RTO5 (Z) *2 P10/INT0/DTTI P17 P06/PWI0 *2 P07/PWO0 *2 6 P00 to P05 *2
P50/PPG2
Waveform generator PWC (ch.0) CMOS I/O port 0, 1, 3, 7, 8 CMOS I/O port 6
P46/PWI1 P47/PWO1
P42/TO0 P41/TIN0
16-bit reload timer (ch.0) 16-bit reload timer (ch.1)
6
P21/TO1 P20/TIN1 P22 to P27
A/D converter (8/10-bit)
16
CMOS I/O port 1, 2, 4, 5, 7
RAM ROM
8-bit D/A converter ROM correction ROM mirroring CMOS I/O port 7
P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 AVR AVCC AVSS P70/DA0/AN8 P71/DA1/AN9
Note : P00 to P07, P10 to P17, P20 to P27 and P30 to P37: With build-in resistors that can be used as input pull-up resistors. *1 : MB90F828B *2 : High current drive pin.
18
DS07-13751-2E
MB90820B Series
MEMORY MAP
FFFFFFH Address #1 Address #1 - 1H ROM area
010000H 00FFFFH Address #2 Address #2 - 1H
ROM area* (FF bank image)
: Internal access memory : Access not allowed
Address #3 + 1H Address #3 000100H 0000FFH 0000F0H 0000EFH 000000H RAM Register area
Peripheral area
* : In Single chip mode, the mirror function is supported.
Parts no. MB90822B MB90823B MB90F822B MB90F823B MB90F828B MB90V820B
Address#1 FF0000H FE0000H FF0000H FE0000H FE0000H (FE0000H)
Address#2 008000H 008000H 008000H 008000H 008000H 008000H
Address#3 0010FFH 0010FFH 0010FFH 0010FFH 0020FFH 0040FFH
Note: The ROM data of bank FF is reflected to the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit is assigned to the same address, enabling reference of the table on the ROM without stating "far". For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 32 K bytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF8000H to FFFFFFH looks, therefore, as if it were the image for 008000H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF8000H to FFFFFFH.
DS07-13751-2E
19
MB90820B Series
F2MC-16LX CPU PROGRAMMING MODEL
* Dedicated registers
AH
AL
: Accumulator (A) Dual 16-bit register used for storing results of calculation etc. The two 16-bit registers can be combined to be used as a sequence of 32-bit register. : User stack pointer (USP) The 16-bit pointer indicating the user stack address. : System stack pointer (SSP) The 16-bit pointer indicating the system stack address. : Processor status (PS) The 16-bit register indicating the system status. : Program counter (PC) The 16-bit register indicating storing location of the current instruction code. : Direct page register (DPR) The 8-bit register indicating bit 8 through 15 of the operand address in executing of the short direct addressing. : Program bank register (PCB) The 8-bit register indicating the program space. : Data bank register (DTB) The 8-bit register indicating the data space. : User stack bank register (USB) The 8-bit register indicating the user stack space. : System stack bank register (SSB) The 8-bit register indicating the system stack space. : Additional data bank register (ADB) The 8-bit register indicating the additional space.
USP
SSP
PS
PC
DPR
PCB
DTB
USB
SSB
ADB
8-bit 16-bit 32-bit
20
DS07-13751-2E
MB90820B Series
* General-purpose registers
Maximum of 32 banks
R7 R5 R3 R1 RW3
R6 R4 R2 R0
RW7 RL3 RW6 RW5 RL2 RW4
RL1 RW2 RW1 RL0 RW0 000180H + (RP x 10H) 16-bit
* Processor status (PS)
ILM RP CCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PS Initial value X ILM2 ILM1 ILM0 0 0 0 B4 0 B3 0 B2 0 B1 0 B0 0 I 0 S 1 T X N X Z X V X C X
: Unused : Undefined
DS07-13751-2E
21
MB90820B Series
I/O MAP
Address Abbreviation Register Byte access Word access Resource name Initial value
000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H to 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H to 00001FH 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H
PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8
Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register
R/W R/W R/W R/W R/W R/W R/W R/W R/W Prohibited area
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8
Port 0 data direction register Port 1 data direction register Port 2 data direction register Port 3 data direction register Port 4 data direction register Port 5 data direction register Port 6 data direction register Port 7 data direction register Port 8 data direction register
R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8
00000000B 00000000B 00000000B 00000000B 00000000B XXXXXX00B 00000000B 00000000B 00000000B
Prohibited area SMR0 SCR0 SIDR0 / SODR0 SSR0 SMR1 SCR1 SIDR1 / SODR1 SSR1 Serial mode register ch.0 Serial control register ch.0 Serial input data register ch.0 / Serial output data register ch.0 Serial status register ch.0 Serial mode register ch.1 Serial control register ch.1 Serial input data register ch.1 / Serial output data register ch.1 Serial status register ch.1 R/W R/W UART ch.0 00000000B 00000100B XXXXXXXXB 00001000B 00000000B 00000100B UART ch.1 XXXXXXXXB 00001000B (Continued)
W, R/W W, R/W R/W R/W
R, R/W R, R/W R/W R/W W, R/W W, R/W R/W R/W
R, R/W R, R/W
22
DS07-13751-2E
MB90820B Series
Address
Abbreviation
Register
Byte access
Word access
Resource name
Initial value
000028H 000029H 00002AH 00002BH 00002CH 00002DH, 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H
PWCSL1 PWCSH1 PWC1 DIV1
PWC control status register ch.1 PWC data buffer register ch.1 Divide ratio control register ch.1
R/W
R/W PWC timer ch.1
00000000B 00000000B XXXXXXXXB XXXXXXXXB XXXXXX00B
R, R/W R, R/W R/W R/W R/W
Prohibited area PCKCR ENIR EIRR ELVRL ELVRH PLL clock control register DTP / Interrupt enable register DTP / Interrupt cause register Request level setting register (lower byte) Request level setting register (higher byte) Clock division ratio control register ch.0 Clock division ratio control register ch.1 PPG down counter register ch.0 PPG cycle setting register ch.0 PPG duty setting register ch.0 PPG control status register ch.0 PPG down counter register ch.1 PPG cycle setting register ch.1 PPG duty setting register ch.1 PPG control status register ch.1 W R/W R/W R/W R/W W R/W R/W R/W R/W PLL XXXX0000B 00000000B XXXXXXXXB DTP/ external interrupt 0 0 0 0 0 0 0 0 B ch.0 to ch.7 00000000B
Prohibited area CDCR0 R/W R/W Communication prescaler ch.0 Communication prescaler ch.1 00XXX000B
Prohibited area CDCR1 PDCR0 PCSR0 PDUT0 PCNTL0 PCNTH0 PDCR1 PCSR1 PDUT1 PCNTL1 PCNTH1 R/W R/W R/W R/W R/W R/W R W W R/W R/W R W W R/W R/W 00XXX000B 11111111B 11111111B XXXXXXXXB 16-bit PPG timer XXXXXXXXB ch.0 XXXXXXXXB XXXXXXXXB XX000000B 00000000B 11111111B 11111111B XXXXXXXXB 16-bit PPG timer XXXXXXXXB ch.1 XXXXXXXXB XXXXXXXXB XX000000B 00000000B (Continued)
DS07-13751-2E
23
MB90820B Series
Address
Abbreviation
Register
Byte Word access access
Resource name
Initial value
000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH 00005EH 00005FH 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H
PDCR2 PCSR2 PDUT2 PCNTL2 PCNTH2 TMRR0 TMRR1 TMRR2 DTCR0 DTCR1 DTCR2 SIGCR CPCLRB / CPCLR TCDT TCCSL TCCSH IPCP0 IPCP1 IPCP2 IPCP3
PPG down counter register ch.2 PPG cycle setting register ch.2 PPG duty setting register ch.2 PPG control status register ch.2 16-bit timer register ch.0 16-bit timer register ch.1 16-bit timer register ch.2 16-bit timer control register ch.0 16-bit timer control register ch.1 16-bit timer control register ch.2 Waveform control register Compare clear buffer register/ Compare clear register Timer data register Timer control status register (lower) Timer control status register (upper) Input capture data register ch.0 Input capture data register ch.1 Input capture data register ch.2 Input capture data register ch.3
R/W R/W R/W R/W R/W R/W R/W R/W
R W 16-bit PPG timer ch.2 W R/W R/W R/W R/W R/W Waveform generator R/W R/W R/W R/W R/W R/W R/W R/W R R 16-bit input capture (ch.0 to ch.3) R R
11111111B 11111111B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XX000000B 00000000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 00000000B 11111111B 11111111B 00000000B 16-bit free-run timer 0 0 0 0 0 0 0 0 B X0100000B 00000000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued)
24
DS07-13751-2E
MB90820B Series
Address
Abbreviation
Register
Byte Word access access
Resource name
Initial value
000068H 000069H 00006AH 00006BH 00006CH to 00006EH 00006FH 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH 000080H 000081H 000082H 000083H 000084H 000085H 000086H
PICSL01 PICSH01 ICSL23 ICSH23
Input capture control status register ch.0,ch.1 (lower) PPG output control / Input capture control status register ch.0,ch.1 (upper) Input capture control status register ch.2,ch.3 (lower) Input capture control status register ch.2,ch.3 (upper)
R/W
R/W
00000000B 00000000B 00000000B XXXXXX00B
R, R/W R, R/W R/W R R/W R
16-bit input capture (ch.0 to ch.3)
Prohibited area ROMM OCCPB0 / OCCP0 OCCPB1 / OCCP1 OCCPB2 / OCCP2 OCCPB3 / OCCP3 OCCPB4 / OCCP4 OCCPB5 / OCCP5 OCS0 OCS1 OCS2 OCS3 OCS4 OCS5 TMCSRL0 TMCSRH0 TMR0 / TMRD0 TMCSRL1 ROM mirroring function selection register Output compare buffer register / Output compare register ch.0 Output compare buffer register / Output compare register ch.1 Output compare buffer register / Output compare register ch.2 Output compare buffer register / Output compare register ch.3 Output compare buffer register / Output compare register ch.4 Output compare buffer register / Output compare register ch.5 Compare control register ch.0 Compare control register ch.1 Compare control register ch.2 Compare control register ch.3 Compare control register ch.4 Compare control register ch.5 Timer control status register ch.0 (lower) Timer control status register ch.0 (upper) 16 bit timer register ch.0 / 16-bit reload register ch.0 Timer control status register ch.1 (lower) W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 16-bit reload timer (ch.1) 16-bit reload timer (ch.0) Output compare (ch.0 to ch.5) ROM mirroring function XXXXXXX1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 1 1 0 0B X1 1 0 0 0 0 0B 0 0 0 0 1 1 0 0B X1 1 0 0 0 0 0B 0 0 0 0 1 1 0 0B X1 1 0 0 0 0 0B 00000000B XXX1 0000B XXXXXXXXB XXXXXXXXB 00000000B (Continued)
DS07-13751-2E
25
MB90820B Series
Address
Abbreviation
Register
Byte access
Word access
Resource name
Initial value
000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH 000090H to 00009DH 00009EH 00009FH 0000A0H 0000A1H 0000A2H to 0000A7H 0000A8H 0000A9H 0000AAH to 0000ADH 0000AEH 0000AFH
TMCSRH1 TMR1 / TMRD1 CSVCR
Timer control status register ch.1 (upper) 16 bit timer register ch.1 / 16-bit reload register ch.1 Clock supervisor control register* Port 0 pull-up resistor setting register Port 1 pull-up resistor setting register Port 2 pull-up resistor setting register Port 3 pull-up resistor setting register
R/W R, R/W Prohibited area
R/W R/W
XXX1 0000B 16-bit reload timer (ch.1) XXXXXXXXB XXXXXXXXB Clock supervisor 00011100B
RDR0 RDR1 RDR2 RDR3
R/W R/W R/W R/W
R/W R/W R/W R/W
Port 0 Port 1 Port 2 Port 3
00000000B 00000000B 00000000B 00000000B
Prohibited area PACSR DIRR LPMCR CKSCR Program address detection control status register Delayed interrupt cause / clear register Low-power consumption mode control register Clock selection register R/W R/W R/W R/W Address match detection XXXX0 0 0 0 B
Delayed interrupt XXXXXXX0B Low-power consumption control register 00011000B 1 1 1 1 1 1 0 0B
W, R/W W, R/W R, R/W R, R/W
Prohibited area WDTC TBTC Watchdog timer control register R, W R, W Watchdog timer Time-base timer XXXXX11 1 B 1 XX0 0 1 0 0 B
Time-base timer control register W, R/W W, R/W Prohibited area
FMCS
Flash memory control status register
R, R/W R, R/W
Flash memory interface circuit
0 0 0 X0 0 0 0 B
Prohibited area (Continued)
26
DS07-13751-2E
MB90820B Series
Address
Abbreviation
Register
Byte access
Word access
Resource name
Initial value
0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H 0000C1H 0000C2H 0000C3H 0000C4H 0000C5H 0000C6H 0000C7H 0000C8H 0000C9H 0000CAH 0000CBH 0000CCH 0000CDH 0000CEH 0000CFH 0000D0H 0000D1H to 0000EFH
ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 PWCSL0 PWCSH0 PWC0 DIV0 ADER0 ADCS0 ADCS1 ADCR0 ADCR1 ADSR0 ADSR1 DAT0 DAT1 DACR0 DACR1 ADER1
Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 PWC control status register ch.0 PWC data buffer register ch.0 Divide ratio control register ch.0 A/D input enable register 0 A/D control status register 0 A/D data register 0 A/D data register 1 A/D setting register 0 A/D setting register 1 D/A data register 0 D/A data register 1 D/A control register 0 D/A control register 1 A/D input enable register 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller Interrupt controller
00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000000B 00000000B PWC timer (ch.0) XXXXXXXXB XXXXXXXXB XXXXXX00B Port 6, A/D 11111111B 000XXXX0B 0 0 0 0 0 0 0 XB 8/10-bit A/D converter XXXXXXXXB XXXXXXXXB 00000000B 00000000B XXXXXXXXB 8-bit D/A converter XXXXXXXXB XXXXXXX0B XXXXXXX0B Port 7, A/D 11111111B
R, R/W R, R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W
A/D control status register 1 W, R/W W, R/W
Prohibited area (Continued)
DS07-13751-2E
27
MB90820B Series
(Continued)
Address Abbreviation Register Byte access Word access Resource name Initial value
0000F0H to 0000FFH 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H PADRL0 PADRM0 PADRH0 PADRL1 PADRM1 PADRH1 Program address detection register 0 (lower) Program address detection register 0 (middle) Program address detection register 0 (higher) Program address detection register 1 (lower) Program address detection register 1 (middle) Program address detection register 1 (higher)
External area R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Address match detection
Address match detection
* : For MB90F828B only. Prohibited for the other products. * Meaning of abbreviations used for reading and writing R/W: Read and write enabled R : Read-only W : Write-only * Explanation of initial values 0 : The bit is initialized to "0". 1 : The bit is initialized to "1". X : The initial value of the bit is undefined.
28
DS07-13751-2E
MB90820B Series
INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt cause
Reset INT9 instruction Exception processing A/D converter conversion complete Output compare ch.0 match End of measurement by PWC timer ch.0 / PWC timer ch.0 overflow 16-bit PPG timer ch.0 Output compare ch.1 match 16-bit PPG timer ch.1 Output compare ch.2 match 16-bit reload timer ch.1 underflow Output compare ch.3 match DTP/ext. interrupt ch.0/ch.1 detection DTTI Output compare ch.4 match DTP/ext. interrupt ch.2/ch.3 detection Output compare ch.5 match End of measurement by PWC timer ch.1 / PWC timer ch.1 overflow DTP/ext. interrupt ch.4 detection DTP/ext. interrupt ch.5 detection DTP/ext. interrupt ch.6 detection DTP/ext. interrupt ch.7 detection Waveform generator 16-bit timers ch.0/ ch.1/ch.2 underflow 16-bit reload timer ch.0 underflow 16-bit free-run timer zero detect 16-bit PPG timer ch.2 Input capture ch.0/ch.1 16-bit free-run timer compare clear Input capture ch.2/ch.3 Time-base timer UART ch.1 receive UART ch.1 send UART ch.0 receive UART ch.0 send Flash memory status Delayed interrupt generator module
EI2OS support
Interrupt vector Number
#08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH
Address
FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H
Interrupt control register ICR Address ICR00
ICR01
Priority
High
0000B0H
0000B1H
ICR02 ICR03
0000B2H 0000B3H
ICR04
0000B4H
ICR05
0000B5H
ICR06
0000B6H
ICR07 ICR08
0000B7H 0000B8H
ICR09
0000B9H
ICR10 ICR11 ICR12 ICR13 ICR14 ICR15
0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH Low
: Can be used and support the EI2OS stop request. : Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal. : Cannot be used. : Usable when an interrupt cause that shares the ICR is not used.
DS07-13751-2E
29
MB90820B Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol VCC Power supply voltage* Input voltage*
1 1 1
Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 - 2.0 -40 -55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 + 2.0 20 15 4 12 100 50 -15 -4 -100 -50 430 +85 +150
Unit V V V V V mA mA mA mA mA mA mA mA mA mA mA mW C C *4
Remarks
AVCC AVR VI VO ICLAMP | ICLAMP | IOL IOLAV1 IOLAV2 IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg
VCC = AVCC *2 AVCC AVR, AVR AVss *3 *3 *5 *5 *4 Except for P00 to P07, P82 to P87 P00 to P07, P82 to P87
Output voltage*
Maximum clamp current Total maximum clamp current "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature
*1 : This parameter is based on VSS = AVSS = 0.0 V. *2 : AVCC must never exceed VCC when the power is turned on. *3 : VI and VO must never exceed VCC + 0.3 V. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : The maximum output current is a peak value for a corresponding pin. (Continued)
30
DS07-13751-2E
MB90820B Series
(Continued) *5 : * * * * * * * * * * * Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50, P51, P80 to P87. Use within recommended operating conditions. Use at DC voltage (current). The +B signal is an input signal exceeding VCC voltage. The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the Vcc pin, and this may affect other devices. Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. Care must be taken not to leave the +B input pin open. Note that analog system input/output pins (LCD drive pins and comparator input pins, etc.) other than the A/D input pins cannot accept +B input. Sample recommended circuits:
Input/output equivalent circuits Protective diode Vcc Limiting resistance +B input (0 V to 16 V) N-ch P-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07-13751-2E
31
MB90820B Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V) Parameter Symbol Pin name Power supply voltage VCC AVCC 3.5 5.5 V Condition Value Min 4.5 Max 5.5 Unit V Remarks At normal operation TA = -40 C to +85 C Normal operation when D/A converter is not used TA = -40 C to +85 C Normal operation when A/D converter and D/A converter are not used TA = -40 C to +85 C Maintains state in stop mode CMOS input
4.0
5.5
V
VIH P30 to P37, P60 to P67 P00 to P07, P10 to P17, P20 to P27, P40 to P44, P45*1, P46, P47, P50, P51, P70, P71, P72*1, P73 to P77, P80 to P87, RST MD0, MD1, MD2
3.0 0.7 VCC
5.5 VCC + 0.3
V V
"H" level input voltage
VIHS
0.8 VCC
VCC + 0.3
V
CMOS hysteresis input
VIHM VIL
VCC = 5 V VCC - 0.3 VCC + 0.3 P30 to P37, P60 to P67 10% VSS - 0.3 0.3 VCC P00 to P07, P10 to P17, P20 to P27, P40 to P44, P45*1, P46, P47, P50, P51, P70, P71, P72*1, P73 to P77, P80 to P87, RST MD0, MD1, MD2
V V
MD input CMOS input
"L" level input voltage
VILS
VSS - 0.3
0.2 VCC
V
CMOS hysteresis input
VILM Smoothing capacitor Reference input voltage of A/D converter Operating temperature CS
VSS - 0.3 VSS + 0.3 0.1 1.0
V F
MD input *2
AVR
2.7
AVCC
V
TA
-40
+85
C
*1 : UART ch.0/ch.1 data input pins P45/SIN0, P72/SIN1/AN10 can be used as CMOS input by the communication prescaler control register (CDRR). *2 : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. On the VCC pin, connect a bypass capacitor that has a larger capacity than that of CS. Refer to the following figure for connection of smoothing capacitor CS. (Continued)
32
DS07-13751-2E
MB90820B Series
(Continued)
* C pin connection circuit
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.
DS07-13751-2E
33
MB90820B Series
3. DC Characteristics
Parameter "H" level output voltage Symbol VOH VOL1 VOL2 Input leakage current Pull-up resistance Pull-down resistance IIL Pin name All output pins (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Condition Unit Remarks Min Typ Max VCC = 4.5 V, IOH = -4.0 mA VCC - 0.5 -5 0.4 0.4 +5 V V V A At pull-up disabled MASK ROM product MASK ROM product (Continued)
"L" level output voltage
All pins except VCC = 4.5 V, P00 to P07 IOL1 = 4.0 mA P82 to P87 P00 to P07 P82 to P87 All input pins P00 to P07, P10 to P17, P20 to P27, P30 to P37, RST MD2 VCC = 4.5 V, IOL2 = 12.0 mA VCC = 5.5 V, VSS < VI< VCC
RUP
25
50
100
k
RDOWN
25
50
100
k
34
DS07-13751-2E
MB90820B Series
(Continued) (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin name Condition VCC = 5.0 V, Internal frequency: 24 MHz, At normal operation VCC = 5.0 V, Internal frequency: 24 MHz, At writing in flash memory VCC = 5.0 V, Internal frequency: 24 MHz, At erasing memory Power supply current* ICCS VCC VCC = 5.0 V, Internal frequency: 24 MHz, At sleep mode VCC = 5.0 V, Internal frequency: 2 MHz, At main timer mode VCC = 5.0 V, Internal frequency: 8 MHz, At timer mode, TA = +25 C In stop mode, TA = +25 C Except AVCC, AVSS, AVR, C, VCC and VSS Value Min Typ 35 45 Max 50 60 Unit Remarks
Parameter
mA MASK ROM product mA Flash memory product
ICC
60
75
mA
Flash memory product

65
80
mA
Flash memory product
mA MASK ROM product 15 25 mA Flash memory product
mA MASK ROM product 0.3 0.8 mA Flash memory product
ICTS
mA MASK ROM product 3 7 mA A 5 20 mA pF Flash memory product MASK ROM product Flash memory product
ICCT
ICCH
Input capacitance
CIN
5
15
* : The power supply current is regulated with an external clock.
DS07-13751-2E
35
MB90820B Series
4. AC Characteristics
(1) Clock Timings (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Symbol Pin name Unit Remarks Min Typ Max 3 3 Clock frequency FC X0, X1 4 4 4 4 4 62.5 Clock cycle time tHCYL X0, X1 41.67 PWH, PWL tCR tCF fCP tCP 333 5 24 666 ns 16 24 24 12 8 6 4 333 ns MHz When using oscillation circuit When using external clock 1 multiplied PLL 2 multiplied PLL 3 multiplied PLL 4 multiplied PLL 6 multiplied PLL When using oscillation circuit When using external clock When using external clock, duty ratio is about 30% to 70%. When using external clock
Parameter
Input clock pulse width
X0
10 1.5 41.67
ns
Input clock rise/fall time Internal operating clock frequency Internal operating clock cycle time
X0
ns MHz ns
tHCYL
X0
PWH tCF PWL tCR
0.8 VCC 0.2 VCC
36
DS07-13751-2E
MB90820B Series
Relationship between internal operating clock frequency and power supply voltage Power supply voltage VCC (V)
Guaranteed D/A Converter operating range
5.5 4.5 4.0 3.5 Normal operation guarantee range Operation guarantee range of PLL
Guaranteed A/D Converter operating range
1.5 4 Internal operating clock frequency fCp (MHz)
24
Relationship between clock frequency and internal operating clock frequency Internal operating clock frequency fCp (MHz) X6 24 X4 X3 X2 X1
16 12 8 4 1.5 34 8 12 16 Clock frequency FC (MHz) 24 Not multiplied
The AC ratings are measured for the following measurement reference voltages
* Input signal waveform * Output signal waveform
Hysteresis input pin
0.8 VCC 0.2 VCC
Output pin
2.4 V 0.8 V
Pins other than hysteresis input/MD input
0.7 VCC 0.3 VCC
DS07-13751-2E
37
MB90820B Series
(2) External Reset (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Unit Remarks Min Max 500 Reset input time tRSTL RST Oscillation time of oscillator* + 100 100 ns s s In normal operation In stop mode In time-base timer mode
Parameter
Symbol
Pin name
* : Oscillation time of oscillator is the time to reach to 90% of the oscillation amplitude from stand still. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In ceramic oscillator, the oscillation time is between hundreds of s to several ms. In the external clock, the oscillation time is 0 ms. * In normal operation mode
tRSTL
RST
0.2 VCC 0.2 VCC
* In stop mode, at power on
tRSTL RST
0.2 VCC
0.2 VCC
90% of the oscillation amplitude X0
Internal operation clock Oscillation time of oscillator 100 s
Oscillator stabilization time Instruction execution Internal reset
38
DS07-13751-2E
MB90820B Series
(3) Power-on Reset (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Symbol Pin name Condition Unit Remarks Min Max tR tOFF VCC VCC 0.05 1 30 ms ms Waiting time for power supply on
Parameter Power supply rising time Power supply cut-off time
tR
VCC
2.7 V 0.2 V 0.2 V tOFF 0.2 V
Note : Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, be sure to set the slope of rising within 50 mV/ms or less as shown below.
VCC 3.0 V VSS
RAM data hold time
Be sure to set the slope of rising within 50 mV/ms or less.
DS07-13751-2E
39
MB90820B Series
(4) UART (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Pin name Condition Unit Min Max SCK0 to SCK1 SCK0 to SCK1 SOT0 to SOT1 SCK0 to SCK1 SIN0 to SIN1 SCK0 to SCK1 SIN0 to SIN1 SCK0 to SCK1 SCK0 to SCK1 SCK0 to SCK1 SOT0 to SOT1 SCK0 to SCK1 SIN0 to SIN1 SCK0 to SCK1 SIN0 to SIN1 CL = 80 pF + 1 TTL for an output pin of external shift clock mode CL = 80 pF + 1 TTL for an output pin of internal shift clock mode 8 tCP -80 100 60 4 tCP 4 tCP 60 60 + 80 150 ns ns ns ns ns ns ns ns ns
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time
Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
Notes : * These are AC ratings in the CLK synchronous mode. * CL is the load capacitance value connected to pins while testing. * tCP is machine cycle time (unit : ns).
40
DS07-13751-2E
MB90820B Series
* Internal shift clock mode
SCK
0.8 V tSLOV 2.4 V
tSCYC 2.4 V 0.8 V
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
* External shift clock mode
SCK
0.2 VCC tSLOV
tSLSH 0.2 VCC
tSHSL 0.8 VCC
0.8 VCC
2.4 V
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
DS07-13751-2E
41
MB90820B Series
(5) Resources Input Timing (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Pin name Condition Unit Min Max IN0 to IN3, TIN0 to TIN1, PWI0 to PWI1, DTTI
Parameter
Symbol
Input pulse width
tTIWH tTIWL
4 tCP
ns
IN0 to IN3, TIN0 to TIN1, PWI0 to PWI1, DTTI
0.8 VCC
0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC
(6) Trigger Input Timing (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Pin name Condition Unit Min Max INT0 to INT7 5 tCP ns
Parameter Input pulse width
Symbol tTRGH tTRGL
0.8 VCC
0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC
INT0 to INT7
42
DS07-13751-2E
MB90820B Series
5. A/D Converter Electrical Characteristics
Parameter Resolution Total error Non-linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Compare time Sampling time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Offset between channels (3.0 V AVR - AVSS, VCC = AVCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Pin CondiSymbol Unit Remarks name tion Min Typ Max VOT VFST IAIN VAIN IA IAH IR IRH -- AN0 to AN15 AN0 to AN15 AN0 to AN15 AN0 to AN15 AVR AVCC AVR AN0 to AN15 AVSS - 1.5 LSB AVR - 3.5 LSB 1.0 2.0 0.5 1.2 - 0.3 AVSS AVSS + 2.7 10 AVSS + 0.5 LSB AVR - 1.5 LSB 2.4 600 3.0 2.5 1.9 AVSS + 2.5 LSB AVR + 0.5 LSB + 0.3 AVR AVCC 4.7 5 900 5 4 bit LSB LSB LSB V V s s s s A V V mA A * A A * LSB 4.5 V < AVcc < 5.5 V 4.0 V < AVcc < 4.5 V 4.5 V < AVcc < 5.5 V 4.0 V < AVcc < 4.5 V
* : The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVR = 5.0 V) Note : The error increases proportionally as |AVR - AVSS| decreases.
DS07-13751-2E
43
MB90820B Series
6. A/D Converter Glossary
: Analog variation that is recognized by an A/D converter. : Deviation between a line across zero-transition line ("00 0000 0000" "00 0000 0001") and full-scale transition line ("11 1111 1110""11 1111 1111") and actual conversion characteristics. Differential linearity error : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value Total error : Difference between an actual value and an ideal value. A total error includes zero transition error, full-scale transition error, and linear error. Resolution Non linearity error
Total error
3FFH 3FEH 3FDH
Actual conversion characteristics
1.5 LSB
Digital output
{1 LSB x (N - 1) + 0.5 LSB}
004H 003H 002H 001H AVSS
VNT
(Measurement value) Actual conversion characteristics Ideal characteristics
0.5 LSB AVR
Analog input VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB AVR - AVss [V] 1024
Total error for digital output N = 1 LSB = (Ideal value)
[LSB]
N : A/D converter digital output value VOT(Ideal value) = AVss + 0.5 LSB [V] VFST(Ideal value) = AVR - 1.5 LSB [V] VNT : Voltage at which of digital output transitions from (N - 1)H to NH. (Continued)
44
DS07-13751-2E
MB90820B Series
(Continued) Linearity error
3FFH 3FEH 3FDH
Differential linearity error
Ideal characteristics
(N + 1)H VFST (Measurement value)
Actual conversion characteristics
{1 LSB x (N - 1) + VOT }
Actual conversion characteristics
Digital output
Digital output
NH
004H 003H 002H 001H AVss
VNT (Measurement value)
V(N + 1)T (N - 1)H
Actual conversion characteristics Ideal characteristics
VOT(Measurement value) AVR
(Measurement value)
VNT
(N - 2)H
(Measurement value) Actual conversion characteristics
AVR
AVss
Analog input Linearity error of = digital output N
Analog input VNT - {1 LSB x (N - 1) + VOT} 1 LSB - 1 [LSB] [V] [LSB]
Differential linearity error V (N + 1) T - VNT = 1 LSB of digital output N 1 LSB = N VFST - VOT 1022
: A/D converter digital output value
VOT : Voltage at which of digital output transmissions from "000H" to "001H". VFST : Voltage at which of digital output transmissions from "3FEH" to "3FFH".
DS07-13751-2E
45
MB90820B Series
7. Notes on Using A/D Converter
* About the external impedance of the analog input and its sampling time * A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. And if the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. * Analog input circuit model
R
Analog input Comparator
C
During sampling : ON R 2.0 k (Max) 2.0 k (Max) C 14.4 pF (Max) 16.0 pF (Max)
MB90822B/823B MB90F822B/F823B Note : The values are reference values.
* The relationship between the external impedance and minimum sampling time (External impedance = 0 k to 100 k)
100 90
(External impedance = 0 k to 20 k)
20 18
External impedance [k]
80 70 60 50 40 30 20 10 0 0
MB90822B/ 823B MB90F822B/F823B
External impedance [k]
16 14 12 10 8 6 4 2 0 0
MB90822B/ 823B MB90F822B/F823B
5
10
15
20
25
30
35
1
2
3
4
5
6
7
8
Minimum sampling time [s]
Minimum sampling time [s]
* About the error The accuracy gets worse as | AVR-AVSS | becomes smaller.
46
DS07-13751-2E
MB90820B Series
8. Electrical Characteristics of D/A convertor
Parameter Resolution Differential linearity error Conversion time Analog output impedance Power supply current (VCC = AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Symbol Pin name Condition Unit Remarks Min Typ Max IDVR IDVRS AVCC 8 0.45 2.9 160 0.1 0.5 3.8 920 bit LSB s k A A D/A stops *
* : With load capacitance 20 pF.
DS07-13751-2E
47
MB90820B Series
9. Flash Memory Program/Erase Characteristics
Parameter Sector erase time Chip erase time Word (16 bit width) programing time Program/Erase cycle Flash data retention time Average TA = +85 C TA = +25 C VCC = 5.0 V Condition Value Min 10,000 20 Typ 1 9 16 Max 15 3,600 Unit s s s cycle year * Remarks Excludes programming prior to erasure Excludes programming prior to erasure Except for the overhead time of the system
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 C) .
ORDERING INFORMATION
Part number MB90F823BPMC MB90F822BPMC MB90822BPMC MB90823BPMC MB90F828BPMC MB90F823BPMC1 MB90F822BPMC1 MB90822BPMC1 MB90823BPMC1 MB90F828BPMC1 MB90F823BPF MB90F822BPF MB90822BPF MB90823BPF MB90F828BPF Package
80-pin plastic LQFP (FPT-80P-M21)
80-pin plastic LQFP (FPT-80P-M22)
80-pin plastic QFP (FPT-80P-M06)
48
DS07-13751-2E
MB90820B Series
PACKAGE DIMENSIONS
80-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight 0.50 mm 12 mm x 12 mm Gullwing Plastic mold 1.70 mm Max 0.47 g P-LFQFP80-12x12-0.50
(FPT-80P-M21)
Code (Reference)
80-pin plastic LQFP (FPT-80P-M21)
14.000.20(.551.008)SQ
* 12.000.10(.472.004)SQ
60 41
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
0.1450.055 (.006.002)
61
40
0.08(.003)
Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
INDEX
80 21
0~8
0.100.05 (.004.002) (Stand off)
"A"
LEAD No.
1
20
0.50(.020)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.25(.010)
0.200.05 (.008.002)
0.08(.003)
M
(c)2006-2008 FUJITSU MICROELECTRONICS LIMITED F80035S-c-2-3 C
2006 FUJITSU LIMITED F80035S-c-2-2
Dimensions in mm (inches). Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued)
DS07-13751-2E
49
MB90820B Series
80-pin plastic LQFP
Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight
0.65 mm 14.00 mm x 14.00 mm Gullwing Plastic mold 1.70 mm Max 0.62 g P-LFQFP80-14x14-0.65
(FPT-80P-M22)
Code (Reference)
80-pin plastic LQFP (FPT-80P-M22)
16.000.20(.630.008)SQ
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
0.1450.055 (.006.002)
41
* 14.000.10(.551.004)SQ
60
61
40
0.10(.004)
Details of "A" part 1.50 -0.10 .059 -.004 (Mounting height) 0.25(.010) INDEX 0~8
21
+0.20 +.008
80
1
20
"A" 0.13(.005)
M
0.65(.026)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.320.05 (.013.002)
C
(c)2007-2008 FUJITSU MICROELECTRONICS LIMITED F80036S-c-1-2
2007 FUJITSU LIMITED F80036S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued)
50
DS07-13751-2E
MB90820B Series
(Continued)
80-pin plastic QFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Code (Reference) 0.80 mm 14.00 x 20.00 mm Gullwing Plastic mold 3.35 mm MAX P-QFP80-14x20-0.80
(FPT-80P-M06)
80-pin plastic QFP (FPT-80P-M06)
23.900.40(.941.016) * 20.000.20(.787.008)
64 41
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
65
40
0.10(.004) 17.900.40 (.705.016)
* 14.000.20 (.551.008)
INDEX Details of "A" part
80 25
0.25(.010) +0.30 3.05 -0.20 +.012 .120 -.008 (Mounting height)
1 24
0.80(.031)
0~8
M
0.370.05 (.015.002)
0.16(.006)
0.170.06 (.007.002) 0.800.20 (.031.008) 0.880.15 (.035.006) 0.30 -0.25
+0.10 +.004
"A"
.012 -.010 (Stand off)
C
2002-2008 FUJITSU MICROELECTRONICS LIMITED F80010S-c-6-6
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/
DS07-13751-2E
51
MB90820B Series
MAIN CHANGES IN THIS EDITION
Page 4 Section PACKAGE AND CORRESPONDING PRODUCTS Change Results Changed the MB90822B (FPT-80P-M21). X : Not available : Available
43
ELECTRICAL CHARACTERISTICS Changed the unit of zero transition voltage and full-scale tran5. A/D Converter Electrical sition voltage. Characteristics mV V ORDERING INFORMATION Added the part number. MB90822BPMC MB90823BPMC
48
The vertical lines marked in the left side of the page show the changes.
52
DS07-13751-2E
MB90820B Series
MEMO
DS07-13751-2E
53
MB90820B Series
MEMO
54
DS07-13751-2E
MB90820B Series
MEMO
DS07-13751-2E
55
MB90820B Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. 151 Lorong Chuan, #05-08 New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm.3102, Bund Center, No.222 Yan An Road(E), Shanghai 200002, China Tel: +86-21-6335-1560 Fax: +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road Tsimshatsui, Kowloon Hong Kong Tel: +852-2377-0226 Fax: +852-2376-3269 http://cn.fujitsu.com/fmc/tw
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited Business & Media Promotion Dept.

▲Up To Search▲

Price & Availability of MB90F822B

	To Download MB90F822B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .